对输入的4位二进制数据,能够根据外部的拨码开关来选择10进制转换、8进制转换还是16进制转换。
这个代码对吗???我运行出来的结果好像有问题
********************************************************************
module B2bdoh(di, typ, shu3, shu2, shu1, shu0);
input [3:0] di;
input [1:0] typ; //00, 二进制输出,01,8进制输出,10,10进制输出,11,16进制输出。
output reg [6:0] shu3,shu2,shu1,shu0;
reg [3:0] do_3bit, do_2bit, do_1bit, do_0bit;//=====================//进制转换
always@(*)
case (typ)
2'b00:
begin
do_3bit = {3'b0, di[3]};
do_2bit = {3'b0, di[2]};
do_1bit = {3'b0, di[1]};
do_0bit = {3'b0, di[0]};
end
2'b01:
begin
do_3bit = {4'b0 };
do_2bit = {4'b0 };
do_1bit = {3'b0, di[3] };
do_0bit = {1'b0, di[2:0]};
end
2'b10:
begin
do_3bit = {4'b0 };
do_2bit = {4'b0 };
do_1bit = {3'b0, di[3] };
do_0bit = {1'b0, di[2:0]};
if (di >= 4'd10)
begin
do_1bit = 4'd1;
do_0bit = di - 4'd10;
end
else
begin
do_1bit = 4'd0;
do_0bit = di;
end
end
2'b11:
begin
do_3bit = {4'b0};
do_2bit = {4'b0};
do_1bit = {4'b0};
do_0bit = {di[3:0]};
end
endcase //7管数码管输出
always@(*)
case (do_0bit)
4'h0:shu0=7'b0000001;
4'h1:shu0=7'b1001111;
4'h2:shu0=7'b0010010;
4'h3:shu0=7'b0000110;
4'h4:shu0=7'b1001100;
4'h5:shu0=7'b0100100;
4'h6:shu0=7'b0100000;
4'h7:shu0=7'b0001111;
4'h8:shu0=7'b0000000;
4'h9:shu0=7'b0000100;
4'ha:shu0=7'b0001000;
4'hb:shu0=7'b1100000;
4'hc:shu0=7'b0110001;
4'hd:shu0=7'b1000010;
4'he:shu0=7'b0110000;
4'hf:shu0=7'b0111000;
default: shu0=7'bx;
endcase
always@(*)
case (do_1bit)
4'h0:shu1=7'b0000001;
4'h1:shu1=7'b1001111;
4'h2:shu1=7'b0010010;
4'h3:shu1=7'b0000110;
4'h4:shu1=7'b1001100;
4'h5:shu1=7'b0100100;
4'h6:shu1=7'b0100000;
4'h7:shu1=7'b0001111;
4'h8:shu1=7'b0000000;
4'h9:shu1=7'b0000100;
4'ha:shu1=7'b0001000;
4'hb:shu1=7'b1100000;
4'hc:shu1=7'b0110001;
4'hd:shu1=7'b1000010;
4'he:shu1=7'b0110000;
4'hf:shu1=7'b0111000;
default: shu1=7'bx;
endcase
always@(*)
case (do_2bit)
4'h0:shu2=7'b0000001;
4'h1:shu2=7'b1001111;
4'h2:shu2=7'b0010010;
4'h3:shu2=7'b0000110;
4'h4:shu2=7'b1001100;
4'h5:shu2=7'b0100100;
4'h6:shu2=7'b0100000;
4'h7:shu2=7'b0001111;
4'h8:shu2=7'b0000000;
4'h9:shu2=7'b0000100;
4'ha:shu2=7'b0001000;
4'hb:shu2=7'b1100000;
4'hc:shu2=7'b0110001;
4'hd:shu2=7'b1000010;
4'he:shu2=7'b0110000;
4'hf:shu2=7'b0111000;
default: shu2=7'bx;
endcase
always@(*)
case (do_3bit)
4'h0:shu3=7'b0000001;
4'h1:shu3=7'b1001111;
4'h2:shu3=7'b0010010;
4'h3:shu3=7'b0000110;
4'h4:shu3=7'b1001100;
4'h5:shu3=7'b0100100;
4'h6:shu3=7'b0100000;
4'h7:shu3=7'b0001111;
4'h8:shu3=7'b0000000;
4'h9:shu3=7'b0000100;
4'ha:shu3=7'b0001000;
4'hb:shu3=7'b1100000;
4'hc:shu3=7'b0110001;
4'hd:shu3=7'b1000010;
4'he:shu3=7'b0110000;
4'hf:shu3=7'b0111000;
default: shu3=7'bx;
endcase
endmodule
***********************************************************
这个代码对吗???我运行出来的结果好像有问题
********************************************************************
module B2bdoh(di, typ, shu3, shu2, shu1, shu0);
input [3:0] di;
input [1:0] typ; //00, 二进制输出,01,8进制输出,10,10进制输出,11,16进制输出。
output reg [6:0] shu3,shu2,shu1,shu0;
reg [3:0] do_3bit, do_2bit, do_1bit, do_0bit;//=====================//进制转换
always@(*)
case (typ)
2'b00:
begin
do_3bit = {3'b0, di[3]};
do_2bit = {3'b0, di[2]};
do_1bit = {3'b0, di[1]};
do_0bit = {3'b0, di[0]};
end
2'b01:
begin
do_3bit = {4'b0 };
do_2bit = {4'b0 };
do_1bit = {3'b0, di[3] };
do_0bit = {1'b0, di[2:0]};
end
2'b10:
begin
do_3bit = {4'b0 };
do_2bit = {4'b0 };
do_1bit = {3'b0, di[3] };
do_0bit = {1'b0, di[2:0]};
if (di >= 4'd10)
begin
do_1bit = 4'd1;
do_0bit = di - 4'd10;
end
else
begin
do_1bit = 4'd0;
do_0bit = di;
end
end
2'b11:
begin
do_3bit = {4'b0};
do_2bit = {4'b0};
do_1bit = {4'b0};
do_0bit = {di[3:0]};
end
endcase //7管数码管输出
always@(*)
case (do_0bit)
4'h0:shu0=7'b0000001;
4'h1:shu0=7'b1001111;
4'h2:shu0=7'b0010010;
4'h3:shu0=7'b0000110;
4'h4:shu0=7'b1001100;
4'h5:shu0=7'b0100100;
4'h6:shu0=7'b0100000;
4'h7:shu0=7'b0001111;
4'h8:shu0=7'b0000000;
4'h9:shu0=7'b0000100;
4'ha:shu0=7'b0001000;
4'hb:shu0=7'b1100000;
4'hc:shu0=7'b0110001;
4'hd:shu0=7'b1000010;
4'he:shu0=7'b0110000;
4'hf:shu0=7'b0111000;
default: shu0=7'bx;
endcase
always@(*)
case (do_1bit)
4'h0:shu1=7'b0000001;
4'h1:shu1=7'b1001111;
4'h2:shu1=7'b0010010;
4'h3:shu1=7'b0000110;
4'h4:shu1=7'b1001100;
4'h5:shu1=7'b0100100;
4'h6:shu1=7'b0100000;
4'h7:shu1=7'b0001111;
4'h8:shu1=7'b0000000;
4'h9:shu1=7'b0000100;
4'ha:shu1=7'b0001000;
4'hb:shu1=7'b1100000;
4'hc:shu1=7'b0110001;
4'hd:shu1=7'b1000010;
4'he:shu1=7'b0110000;
4'hf:shu1=7'b0111000;
default: shu1=7'bx;
endcase
always@(*)
case (do_2bit)
4'h0:shu2=7'b0000001;
4'h1:shu2=7'b1001111;
4'h2:shu2=7'b0010010;
4'h3:shu2=7'b0000110;
4'h4:shu2=7'b1001100;
4'h5:shu2=7'b0100100;
4'h6:shu2=7'b0100000;
4'h7:shu2=7'b0001111;
4'h8:shu2=7'b0000000;
4'h9:shu2=7'b0000100;
4'ha:shu2=7'b0001000;
4'hb:shu2=7'b1100000;
4'hc:shu2=7'b0110001;
4'hd:shu2=7'b1000010;
4'he:shu2=7'b0110000;
4'hf:shu2=7'b0111000;
default: shu2=7'bx;
endcase
always@(*)
case (do_3bit)
4'h0:shu3=7'b0000001;
4'h1:shu3=7'b1001111;
4'h2:shu3=7'b0010010;
4'h3:shu3=7'b0000110;
4'h4:shu3=7'b1001100;
4'h5:shu3=7'b0100100;
4'h6:shu3=7'b0100000;
4'h7:shu3=7'b0001111;
4'h8:shu3=7'b0000000;
4'h9:shu3=7'b0000100;
4'ha:shu3=7'b0001000;
4'hb:shu3=7'b1100000;
4'hc:shu3=7'b0110001;
4'hd:shu3=7'b1000010;
4'he:shu3=7'b0110000;
4'hf:shu3=7'b0111000;
default: shu3=7'bx;
endcase
endmodule
***********************************************************