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H27U8G8T2BTR-BC

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H27(U_S)4G8_6F2D series is a 512Mx8bit with spare 16Mx8 bit capacity.
H27(u_s)4g8_6f2d系列是一个512mx8bit备用16Mx8位能力。
The device is offered in 3.0/1.8 Vcc Power Supply, and with x8 and x16 I/O interface
该装置是在3 / 1.8的VCC电源提供,并与X8和X16的I/O接口
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
它的NAND单元为固态大容量存储市场提供了最具成本效益的解决方案。
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
内存分为可以独立擦除的块,因此可以在保存旧数据的同时保存数据。
data is erased.
数据被删除。
The device contains 4096 blocks, composed by 64 pages.
该设备包含4096个区块,由64页组成。
Memory array is split into 2 planes, each of them consisting of 2048 blocks.
内存数组被分成2个平面,每个平面由2048个块组成。
Like all other 2KB - page NAND Flash devices, a program operation allows to write the 2112-byte page in typical
像所有其他2kb页的NAND闪存设备,操作允许一个程序在典型的2112字节的页写
200us(3.3V) and an erase operation can be performed in typical 3.5ms on a 128K-byte block.
200us(3.3V)和擦除操作可以执行在一个典型的3.5ms 128K字节块。
In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages at a time (one per each plane)
除此之外,由于多平面架构,一次可以编写2个页面(每一个平面一个)。
or to erase 2 blocks at a time (again, one per each plane). As a consequence, multi-plane architecture allows program
或者一次擦除2个块(每一个平面上又有一个)。因此,多平面架构允许程序。
time to be reduced by 40% and erase time to be reduction by 50%. In case of multi-plane operation, there is small degradation
时间减少40%,擦除时间减少50%。在多平面操作时,有小的退化。
at 1.8V application in terms of program/erase time.
在1.8V的编程/擦除时间方面的应用。
The multiplane operations are supported both with traditional and ONFI 1.0 protocols.
多平面手术都是与传统和ONFI 1支持的协议。
Data in the page can be read out at 25ns (3V version) and 45nsec (1.8V version) cycle time per byte. The I/O pins
在页面中的数据可以读出为25ns(3V版)和45nsec(1.8版)周期,每字节。输入输出引脚
serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin
用作地址和数据输入/输出端口,以及命令输入。此接口允许减少引脚。
count and easy migration towards different densities, without any rearrangement of footprint.
计数和容易迁移到不同的密度,没有任何重排的足迹。
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
命令、数据和地址同步引入CE #,我们#,ALE和CLE输入引脚。
The on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition,
片上程序/擦除控制器自动控制所有读、程序和擦除功能,包括脉冲重复,
where required, and internal verification and margining of data.
在需要的地方,和内部核查和数据裕。
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