回复：FPGA verilog 提问帖任何问题可以来这里提

求大神帮忙详细分析一下此程序：
/********锯齿波************************************/
module j_b(
input clk,
input rst,
input [3:0]Open,
input [3:0]Frequency,
output [11:0]out_j_d
);
/************************************************/
reg [17:0] cnt;//4096计数器
reg [11:0] rout_d;
always @ (posedge clk,negedge rst)
begin
if(!rst)
begin
cnt<=18'd0;
rout_d<=12'd0;
end
else if(Open==4'd4)//检测是否开启锯齿波
begin
if(cnt>=18'd81920)
begin
cnt<=18'd0;
rout_d<=12'd0;
end
else
begin
cnt<=cnt+Frequency+4'd5;//可变计数器
rout_d<=cnt;
end
end
else
begin
cnt<=18'd0;
rout_d<=12'd0;
end
end
/***************************************************************/
assign out_j_d=rout_d;
endmodule

求助大神能帮忙解读一下，下面这段程序吗？尤其是计数器部分。这是一个音乐播放器设计，但不是很完整，只能播放部分乐谱，本人比较菜，就算是修改了部分程序仍然无法播放完整歌曲，求大神能帮忙完善，让其变成完整的类似于MP3具有切换功能的播放器。
[source lang="verilog"]
module music_top
(
input clk,
input rst_n,
input key1,
output reg buzzer,
output [3:0]led
) ;
parameter CLK_FRE = 50 ;
parameter music_len = 32'd62;
wire [19:0] cycle ;
reg [31:0] play_cnt ;
reg [31:0] music_cnt ;
reg [19:0] hz_cnt ;
wire [4:0] hz_sel ;
wire [7:0] rom_hz_data ;
wire [7:0] rom_time_data ;
reg [31:0] music_time ;
wire button_negedge ;
wire clk_show;
parameter IDLE = 2'd0 ;
parameter PLAY = 2'd1 ;
parameter PLAY_WAIT = 2'd2 ;
parameter PLAY_END = 2'd3 ;
reg [1:0] state ;
reg [1:0] next_state ;
always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
state <= IDLE ;
else
state <= next_state ;
end
always @(*)
begin
case(state)
IDLE : begin
if (button_negedge)
next_state <= PLAY ;
else
next_state <= IDLE ;
end
PLAY : begin
if (play_cnt == music_time)
next_state <= PLAY_WAIT ;
else
next_state <= PLAY ;
end
PLAY_WAIT : begin
if (music_cnt == music_len - 1)
next_state <= PLAY_END ;
else
next_state <= PLAY ;
end
PLAY_END : next_state <= IDLE ;
default : next_state <= IDLE ;
endcase
end
ax_debounce ax_debounce_a0
(
.clk (clk),
.rst (~rst_n),
.button_in (key1),
.button_posedge (),
.button_negedge (button_negedge),
.button_out ()
);
//play counter
always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
music_time <= 32'hffff_ffff ;
else
music_time <= rom_time_data*(CLK_FRE*1000000/96) ;
end
//counter in every step, maximum value is cycle
always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
hz_cnt <= 20'd0 ;
else if (state == PLAY || state == PLAY_WAIT)
begin
if (hz_cnt == cycle - 1)
hz_cnt <= 20'd0 ;
else
hz_cnt <= hz_cnt + 1'b1 ;
end
else
hz_cnt <= 20'd0 ;
end
//buzzer out
always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
buzzer <= 1'b1 ;
else if (state == PLAY || state == PLAY_WAIT)
begin
if (hz_cnt < cycle/24) //duty cycle to adjust buzzer volume
buzzer <= 1'b0;
else
buzzer <= 1'b1;
end
else if (state == IDLE || state == PLAY_END)
buzzer <= 1'b1 ;
end
//play counter
always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
play_cnt <= 32'd0 ;
else if (state == PLAY)
play_cnt <= play_cnt + 1'b1 ;
else
play_cnt <= 32'd0 ;
end
//music step counter
always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
music_cnt <= 32'd0 ;
else if (state == PLAY_WAIT)
music_cnt <= music_cnt + 1'b1 ;
else if (state == IDLE || state == PLAY_END)
music_cnt <= 32'd0 ;
end
//select cycle value with each music value
music_hz
(
.hz_sel(rom_hz_data),
.cycle(cycle)
) ;
//music step value rom
music_rom
(
.address(music_cnt[8:0]),
.clock(clk),
.q(rom_hz_data)
);
//music time value rom
music_time_rom time_rom
(
.address(music_cnt[8:0]),
.clock(clk),
.q(rom_time_data)
);
freq freq(
.clk(clk),
.rst_n(rst_n),
.clk_show(clk_show)
);
led(
.clk(clk_show),
.rst_n(rst_n),
.led(led)
);
endmodule
[/source]

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